FFXI Haven - Ваш Источник #1.

Develop ladder logic that will cycle the cylinder in and out repeatedly, and watch for failure.

plc timers -9.32

9.10 PRACTICE PROBLEM SOLUTIONS

1. edge triggered means the event when a logic signal goes from false to true (positive edge) or from true to false (negative edge).
2. no, but they are essential for retentive timers, and very important for counters.
3. these are limited by the 16 bit number for a range of -32768 to +32767
4. the un underflow bit. This may result in a fault in some PLCs.
5. first pass

motor stop

start motor

start stop

motor

motor
plc timers -9.33
7.
RTF
A Timer T4:0 Time Base 0.01 (DN)
Preset 350
Accum. 0 (EN)
plc timers -9.34
8.
RTO
A Timer T4:0 (DN)
Time Base 1.0 Preset 10 (EN)
Accum. 1

TOF
A Timer T4:1 Time Base .01 (EN)
Preset 50
Accum. 0 (DN)

T4:1 EN

T4:1 TT T4:1 DN

T4:1 Accum. 0 15 45 150 200
A

plc timers -9.36

12.

I/1

O/01

TON

B3/0 T4:0 delay 15 sec

T4:0/DN

13.